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Physical Design Engineer
$151,091
per year
Automation
Scripting
physical design
Power Analysis
VLSI
Static Timing Analysis
Calibre
Microprocessor
PnR
Floor Planning
Clock Tree Synthesis
Layout Verification
Logic Design
Electronic Engineering
Job Description
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for all phases of design for high performance microprocessors from register transfer language (RTL) to final GDSII delivery. Perform front end implementation tasks such as structured data path design, synthesis, logic equivalence check, and static timing analysis (STA) to ensure design is meeting performance requirements with targeted timing constraints using industry standard timing signoff tools like primetime. Collaborate with RTL team, by analyzing design and providing detailed feedback, to perform feasibility analysis on suggested microarchitectures, including performance, area, timing, power, complexity, and effort. Generate timing constraints for synthesis, place and route (PnR) and STA tools to do the design timing closure. Perform Place and Route (PnR) by using industry standard tool for floor planning, logic placement, clock tree creation, timing, area and power optimization to meet timing, area and power constraints for meeting design spec. Generate and implement Engineering Change Orders (ECOs) to fix timing and power for by using timing closure tool, primetime and place and route tool. Run physical design verification flow and fix layout versus schematic (LVS) and design rule checker (DRC) violations for making sure design is meeting foundry rule requirements using Calibre tool. Run electrical analysis to do static and dynamic voltage analysis, logic equivalence check for design verification post PnR. Collaborate with Computer-Aided Design (CAD) team to develop physical design methodologies to automate flows and improve overall design quality for power, performance and area improvement. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,091 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master's degree or foreign equivalent in Electrical Engineering, Electronic Engineering, Computer Engineering or related field and 1 year of experience in job offered or related occupation. 1 year of experience with each of the following skills is required: Utilizing very-large-scale integration (VLSI) design and experience understanding logic design, data path analysis and digital design flow. Experience in floor planning, placement and optimization, clock tree construction, timing analysis, design routing and physical verification, using PnR and PDV (Calibre) CAD tools. Experience performing automation, writing scripts and implementing design, using tool command language (TCL) and shell scripting. Experience in Power, Performance and Area analysis Analyzing Static timing and Static & Dynamic voltage Experience in Physical verification, and experience in layout versus schematic checks.
N/A
Description
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for all phases of design for high performance microprocessors from register transfer language (RTL) to final GDSII delivery. Perform front end implementation tasks such as structured data path design, synthesis, logic equivalence check, and static timing analysis (STA) to ensure design is meeting performance requirements with targeted timing constraints using industry standard timing signoff tools like primetime. Collaborate with RTL team, by analyzing design and providing detailed feedback, to perform feasibility analysis on suggested microarchitectures, including performance, area, timing, power, complexity, and effort. Generate timing constraints for synthesis, place and route (PnR) and STA tools to do the design timing closure. Perform Place and Route (PnR) by using industry standard tool for floor planning, logic placement, clock tree creation, timing, area and power optimization to meet timing, area and power constraints for meeting design spec. Generate and implement Engineering Change Orders (ECOs) to fix timing and power for by using timing closure tool, primetime and place and route tool. Run physical design verification flow and fix layout versus schematic (LVS) and design rule checker (DRC) violations for making sure design is meeting foundry rule requirements using Calibre tool. Run electrical analysis to do static and dynamic voltage analysis, logic equivalence check for design verification post PnR. Collaborate with Computer-Aided Design (CAD) team to develop physical design methodologies to automate flows and improve overall design quality for power, performance and area improvement. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,091 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Minimum Qualifications
Master's degree or foreign equivalent in Electrical Engineering, Electronic Engineering, Computer Engineering or related field and 1 year of experience in job offered or related occupation. 1 year of experience with each of the following skills is required: Utilizing very-large-scale integration (VLSI) design and experience understanding logic design, data path analysis and digital design flow. Experience in floor planning, placement and optimization, clock tree construction, timing analysis, design routing and physical verification, using PnR and PDV (Calibre) CAD tools. Experience performing automation, writing scripts and implementing design, using tool command language (TCL) and shell scripting. Experience in Power, Performance and Area analysis Analyzing Static timing and Static & Dynamic voltage Experience in Physical verification, and experience in layout versus schematic checks.
Preferred Qualifications
N/A
Company Information
Location: Cupertino, CA
Type: Hybrid
Badges:
Changemaker
Flexible Culture